The present invention relates to a memory system comprising a memory module on which a plurality of memory devices are mounted and a memory controller, particularly to data write control in the memory system.
In general, in memory systems such as SDR, DDR-I, and DDR-II, in consideration of time to decode a write command in a memory device, data write latency is set indicating the number of clocks from when the write command is inputted into the memory device until write data starts to be taken in. In this system, a memory controller sends the write command. On the other hand, in consideration of the data write latency, after elapse of a predetermined number of clocks from the write command, the controller sends the write data onto a data bus (DQ bus). Subsequently, on receiving the write command, the memory device uses the write command as a count start point to count the number of clocks corresponding to the data write latency, and starts taking in the write data propagated on the DQ bus from a point at which the counting has ended.
In general, a plurality of memory devices are mounted on a memory module. Therefore, unless a wiring on the memory module is an isometric wiring, a transmission path length of the write command to each memory device differs. As a result, a difference is generated in a timing at which the write command outputted from the memory controller reaches each memory device. Moreover, different memory modules also have a difference in the transmission path length on a mother board. Therefore, the difference is generated in the timing at which the write command reaches each memory device. This difference of the reach timing of the write command, that is, the difference of command propagation delay in the memory module or memory system becomes remarkable with an increase of the number of memory devices mounted on the memory module.
The difference of the command propagation delay sometimes causes a problem that a clock domain is exceeded with a high clock frequency. This will be described hereinafter. In the following, a command/address signal is referred to as a C/A signal, and a bus for transmitting the C/A signal is referred to as a C/A bus. Particularly, the C/A bus to the memory module from the memory controller is referred to as an external C/A bus, and the C/A bus on the module is referred to as an internal C/A bus For example, the use of a single T-branch will be described including a one-stage hierarchy structure which is topology of the bus of the C/A signal on the memory module. In this case, a clock at a time when the write command reaches the memory device closest, to a branch point sometimes differs from a clock at a time when the write command reaches the memory device farthest from the branch point. In this case, as in a related art, an input start point of the write data is defined only by the number of clocks from the write command. Then, a deviation is generated between an original data start time and a point at which the memory device starts taking in the write data, and an erroneous operation is sometimes caused.
Particularly in the memory system, the C/A bus, DQ bus, and clock bus are disposed independently of one another. For a data write operation, an operation has been proposed in which a transmission path of the write command to the memory device from the memory controller is different from a transmission path of the write data. In this memory system, a possibility that the erroneous operation is caused further increases.
The following technique has been proposed with respect to the problem. A register is disposed on the memory module, the latency is set to be variable, and the number of clocks from when the write command is inputted until the write data starts to be inputted is controlled on a register side. However, for the reason that a control content is complicated, there has been a demand for another method which can solve the above-described problem.
An object of the present invention is to provide a memory system in which a plurality of memory devices can appropriately start taking in data regardless of register control and a method for the system.
The present invention is based on the following idea. A clock count start point for taking in write data is set to a newly defined write flag reach point, not a write command reach point in a memory device as in the related art. Thereby, a degree of freedom in bus constitution can be raised. This write flag is used, and especially transmission paths of the write flag and write data to each memory device are constituted of the same topology. Then, a phase relation between the write flag and write data in each memory device becomes constant. Therefore, the above-described problem by the propagation delay of write command can be avoided. Moreover, since the write flag is used to raise the degree of freedom of the bus constitution, the transmission paths of the write command and write flag can also be constituted of the same topology. If possible, output timings can be considered to be adjusted on a memory controller side.
Based on this idea, the present invention provides the following data writing methods and memory systems.
That is, according to the present invention, there is provided a first data writing method in a memory system including a memory module on which a plurality of memory devices are mounted and a memory controller which executes a write control with respect to the memory devices. In the first data writing method, a write flag is defined, and the memory device is constituted to hold a predetermined number of clocks and to count the predetermined number of clocks in response to the write flag. To execute the write control, the memory controller successively inputs write command, write flag, and write data into the memory device. Thereby, the memory device uses a point at which the predetermined number of clocks have elapsed from write flag input as a start point for taking in the write data.
A second data writing method according to the present invention is applied to the first data writing method. In the second data writing method, the memory system is constituted so that a transmission path of the write flag to the memory device from the memory controller has the same topology as that of a transmission path of the write data to the memory device from the memory controller.
A third data writing method according to the present invention is applied to the second data writing method. In the third data writing method, the write data and write flag are directly inputted into the plurality of memory devices from the memory controller.
A fourth data writing method according to the present invention is applied to the third data writing method. In the fourth data writing method, a regulator for temporarily holding the write command on the memory module is mounted, and an internal bus for transmitting the write command to the plurality of memory devices from the regulator is mounted. The write command is inputted into the memory device from the memory controller via the regulator and internal bus.
A fifth data writing method according to the present invention is applied to the first data writing method. In the fifth data writing method, the memory system is constituted so that the transmission path of the write flag to the memory device from the memory controller has a topology different from that of the transmission path of the write data to the memory device from the memory controller.
A sixth data writing method according to the present invention is applied to the fifth data writing method. In the sixth data writing method, the write data is directly inputted into the plurality of memory devices from the memory controller.
A seventh data writing method according to the present invention is applied to the sixth data writing method. In the seventh data writing method, a regulator for temporarily holding the write command and write flag on the memory module is mounted, and first and second internal buses for transmitting the write command and write flag to the plurality of memory devices from the regulator are mounted. The write command and write flag are inputted into the memory device from the memory controller via the regulator and first and second internal buses.
Moreover, according to the present invention, there is provided the following first memory system. The first memory system includes a memory controller which outputs a write flag, write command, and write data. The first memory system further includes a memory module including a plurality of memory devices which hold a predetermined number of clocks and which enter a waiting state of the write flag on receiving the write command and which start taking in the write data from a point of elapse of the predetermined number of clocks from the write flag on receiving the write flag.
A second memory system according to the present invention is applied to the first memory system. In the second memory system, a first transmission path which is a transmission path of the write flag to the memory device from the memory controller has the same topology as that of a second transmission path which is a transmission path of the write data to the memory device from the memory controller.
A third memory system according to the present invention is applied to the second memory system. In the third memory system, the first transmission path includes DQ buses connected to the plurality of memory devices, and the second transmission path includes a WFLG signal line connected to the plurality of memory devices.
A fourth memory system according to the present invention is applied to the third memory system. The fourth memory system further includes an external command/address bus which transmits a command/address signal including the write command to the memory module from the memory controller. The memory module includes a regulator for temporarily holding the command/address signal, and an internal command/address bus for distributing the command/address signal to the respective memory devices from the regulator. The transmission path of the write command to the memory device from the memory controller includes the external command/address bus, regulator, and internal command/address bus, and includes a topology different from that of the first and second transmission paths.
A fifth memory system according to the present invention is applied to the first memory system. In the fifth memory system, a first transmission path which is a transmission path of the write flag to the memory device from the memory controller has a topology different from that of the second transmission path which is a transmission path of the write data to the memory device from the memory controller.
A sixth memory system according to the present invention is applied to the fifth memory system. The sixth memory system further includes an external command/address bus and WFLG signal line for transmitting the command/address signal including the write command, and the write flag to the memory module from the memory controller, and a plurality of DQ buses for transmitting the write data to the plurality of memory devices from the memory controller. The second transmission path includes a plurality of DQ buses.
A seventh memory system according to the present invention is applied to the sixth memory system. In the seventh memory system, the memory module includes a regulator for temporarily holding the command/address signal and write flag, and an internal command/address bus and internal WFLG bus for distributing the command/address signal and write flag to each memory device from the regulator. The first transmission path includes the WFLG signal line, regulator, and internal WFLG bus. The transmission path of the write command to the memory device from the memory controller has a topology which is the same as that of the first transmission path and which is different from that of the second transmission path.
Furthermore, according to the present invention, there is provided the following memory module. On the memory module, a plurality of memory devices are mounted for use in a memory system including a memory controller for outputting a write command, write flag, and write data for a data write operation. In the present memory module, each of the plurality of memory devices enters a waiting state of the write flag on receiving the write command from the memory controller. Each of the plurality of memory devices starts counting a predetermined number of clocks from the write flag which is used as a count start point on receiving the write flag, and starts taking in the write data from a point at which the predetermined number of clocks have been counted.
Additionally, according to the present invention, there is provided the following memory controller. The present memory controller includes a command output portion for outputting a write command, and a write flag output portion for outputting a write flag which corresponds to the write command and which indicates a count start point for counting clocks to specify a taking-in start point of the write data in the memory device. The present memory controller further includes a data output portion for outputting the write data corresponding to the write command after elapse of a predetermined time in consideration of write data latency from when the write flag output portion outputs the write flag.